Сумматор переноса пульсации в vhdl

привет, я пытаюсь сделать 4-битный сумматор переноса пульсаций с VHDL. Проблема в том, что я пытаюсь сделать тестовый стенд, чтобы смоделировать его в ModelSim, но он не работает. Это код, а также код, сообщенный ModelSim:

Полный код сумматора:

library ieee;
use ieee.std_logic_1164.all;


entity fullAdder is
    port( -- Input of the full-adder
            a   : in std_logic;
            -- Input of the full-adder
            b   : in std_logic;
            -- Carry input 
            c_i : in std_logic;
            -- Output of the full-adder
            o   : out std_logic;
            -- Carry output
            c_o : out std_logic
        );
end fullAdder;
architecture data_flow of fullAdder is

 begin

  o   <= a xor b xor c_i;
  
  c_o <= (a and b) or (b and c_i) or (c_i and a);

  end data_flow;

Код переноса пульсаций:

library ieee;
use ieee.std_logic_1164.all;


 entity Ripple_Carry_Adder is 
 Port (
  A: in std_logic_vector (3 downto 0);
  B:in std_logic_vector (3 downto 0);
  Cin:in std_logic;
  S:out std_logic_vector(3 downto 0);
  Cout:out std_logic
 );
 end Ripple_Carry_Adder;

 architecture data_flow2 of Ripple_Carry_Adder is 
 component fullAdder
 Port(
 A:in std_logic;
 B:in std_logic;
 Cin:in std_logic;
 S:out std_logic;
 Cout:out std_logic
 );
 end component;
 signal c1,c2,c3:STD_LOGIC;
 begin
 FA1:fullAdder port map(A(0),B(0), Cin, S(0), c1);
 FA2:fullAdder port map(A(1),B(1), c1, S(1), c2);
 FA3:fullAdder port map(A(2),B(2), c2, S(2), c3);
 FA4:fullAdder port map(A(3),B(3), c3, S(3), Cout);
 end data_flow2;

код тестового стенда Ripple Carry Adder:

            library IEEE;
            use IEEE.STD_LOGIC_1164.ALL;
            use IEEE.STD_LOGIC_UNSIGNED.ALL;
            use IEEE.NUMERIC_STD.ALL;
            ENTITY ripple_carry_adder_tb is
            end ripple_carry_adder_tb;

            ARCHITECTURE behavior OF ripple_carry_adder_tb is
                constant T_CLK   : time := 10 ns; -- Clock period
                constant T_RESET : time := 25 ns; -- Period before the reset deassertion
                COMPONENT Ripple_Carry_Adder
                    PORT (
                        A:in std_logic_vector(3 downto 0);
                        B:in std_logic_vector(3 downto 0);
                        Cin:in std_logic;
                        S:out std_logic_vector(3 downto 0);
                        Cout:out std_logic
                    );
                END COMPONENT;
                
                signal A_tb:std_logic_vector(3 downto 0):="0000";
                signal B_tb:std_logic_vector(3 downto 0):="0000";
                signal Cin_tb:std_logic:='0';
                signal S_tb:std_logic_vector(3 downto 0);
                signal Cout_tb:std_logic;
                
                signal clk_tb : std_logic := '0'; -- clock signal, intialized to '0' 
                signal rst_tb  : std_logic := '0'; -- reset signal  
                signal end_sim : std_logic := '1';
                
                BEGIN
                    clk_tb <= (not(clk_tb) and end_sim) after T_CLK / 2;  -- The clock toggles after T_CLK / 2 when end_sim is high. When end_sim is forced low, the clock stops toggling and the simulation ends.
                    rst_tb <= '1' after T_RESET;
                    RP_1: Ripple_Carry_Adder PORT MAP(A=>A_tb,B=>B_tb,Cin=>Cin_tb,S=>S_tb,Cout=>Cout_tb);
                d_process: process(clk_tb, rst_tb) -- process used to make the testbench signals change synchronously with the rising edge of the clock
                    variable t : integer := 0; -- variable used to count the clock cycle after the reset
                  begin
                    if(rst_tb = '0') then
                      A_tb  <= "0000";
                      B_tb  <= "0000";
                      Cin_tb<='0';
                      t := 0;
                    elsif(rising_edge(clk_tb)) then
                      A_tb<=A_tb+1;
                      B_tb<=B_tb+1;
                      t := t + 1;
                      if (t>32) then
                        end_sim <= '0';
                      end if;
                    end if;
                  end process;
            END;

и это ошибки, о которых сообщает ModelSim, когда я пытаюсь начать симуляцию:

# ** Fatal: (vsim-3817) Port "c_i" of entity "fulladder" is not in the component being instantiated.
#    Time: 0 ns  Iteration: 0  Instance: /ripple_carry_adder_tb/RP_1/FA1 File: 
C:/Users/utente/Desktop/full_adder.vhd Line: 11
# FATAL ERROR while loading design
# Error loading design

Почему не работает? Спасибо